Design And Reuse SoC News Alert

June 1, 2004

Welcome to issue of June 1, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

NEW ON D&R WEB SITE !!!!

D&R FOUNDRY CORNER : All the information you need about silicon proven virtual components and foundry opportunities
Go to: http://www.us.design-reuse.com/foundry

CoreConnect(TM) Audio Input from Coreworks

True Random Number Generator from Athena

Nios II family of 32-bit RISC embedded processors from Altera

Standalone Capless Regulator from ChipIdea Microelectronics

Serial ATA Verification IP from HDL Design House

802.11a Physical Layer from Cranes Software

IP Core of Statistical Test Suite of FIPS 140-2

IP expectations (by Melissa Jones, President, Ultimodule)

Standards-based IP (by Michael Kaskowitz, President, VSI Alliance)

What's needed for mixed-signal verification (by Bijan Kiani, Synopsys VP of Marketing)

IP/SOC PRODUCTS

FlexEOS Embedded FPGAs from M2000 Now Production Ready in 0.13um

LSI Logic Unveils Industry's Highest Speed DDR-2 SDRAM Physical Layer Memory Interface

IPextreme First to Apply Extreme Programming to IP Development for Quality, Reliability

Faraday's USB 2.0 OTG IP Cores Receive USB-IF OTG Compliance Certifications

TAK'ASIC to showcase blazing fast system-on-chip printer solution for Computex IT show

Skyworks Offers Licenses To Revolutionary SMV Technology

Verisity and Cascade Semiconductor Solutions Team to Reduce Risk, Increase Quality for PCI Express Designs

Virtual Silicon Expands Application-Specific I/O Offering

STRUCTURED ASIC

eASIC Announces Tape-out of First Structured ASIC Array

FOUNDRIES

UMC Shareholders Approve NT$0.8 Stock Dividend for Fiscal Year 2003

UMC Announces a Device Technique that Enhances Silicon-on-Insulator (SOI) Transistor Performance

BUSINESS

French startup tackles SoCs for emerging WiMAX market

eASIC Raises $5 Million in Third Round of Funding from Kleiner Perkins Caufield & Byers

AccelChip and Leopard Logic Join Forces to Target DSP Market with Configurable Logic Devices

FSA Announces Worldwide Public Fabless Revenue Growth of 37 Percent Year-Over-Year in Q1 2004

LEGAL

Zoran Names Additional Defendants In Patent Infringement Claim Against MediaTek In District Court

DEALS

ARM Signs 3 Year Purchase Agreement With Verisity For Verification Solutions

EMBEDDED SYSTEMS

Agere Systems Announces 802.11G Wi-Fi Mini-Module Designed for Handheld Consumer Electronics

EZchip's NP-1c Network Processor is Certified by The Tolly Group for Passing IPv6, IPv4 and MPLS Industry Benchmarks

FPGA/CPLD

Xilinx Simplifies QDR II SRAM Memory Interfacing With New Virtex-II PRO Memory Tool Kit

EDA

Faraday Adopts Incentia for ASIC Synthesis & Timing Flow

Sequence Validates MSIM from Legend Design for Accuracy of Power and Signal Integrity Analysis

OTHER

VSIA group shakes up its foundations

NEW ON D&R WEB SITE

View webcasts from the 2003 IP/SoC Forum:
- Keynote talk from Dr. Raul Camposano Senior VP, CTO - Synopsys
- Panel on ASIC Platform (brought to you by LSI Logic)
- Panel on IP Quality & Verification (brought to you by Verisity)
- Panel on SystemC (brought to you by CoWare)
Go to: http://www.us.design-reuse.com/exclusive

DAC 2004
San Diego, CA
June 7-11, 2004
Booth 1420
Contact D&R

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D&R Verification IP Catalog :
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